Micron Maps a New Decade of DRAM, HBM and NAND
Micron presented a multi-year memory roadmap spanning 1δ DRAM, DDR6, LPDDR6, vertical HBM, vEIM, 3D DRAM and G11 NAND. The company plans to introduce wafer bonding with 1ε, High-NA EUV in later generations, and more than 400 layers for G11 NAND, whose production ramp is targeted for the second half of 2027. Micron claims DDR6 will deliver more than twice DDR5 bandwidth and LPDDR6 will improve power efficiency by 35%, but the supplied reports contain no independent validation.
The roadmap directly affects AI infrastructure because it combines higher-bandwidth memory, processor-level integration and denser NAND, while also showing that Micron is choosing a different DRAM scaling path from rivals pursuing 4F² cells.
Having jettisoned 4F2 memory cells from its roadmap, Micron must use different methods to continue scaling its DRAM devices in the coming years to keep up with rivals planning to use smaller DRAM transistors towards the end of the decade. Instead, Micron intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography for subsequent generations. Meanwhile, the company is developing new types of memory, including vertical high-bandwidth memory (vHBM) and vertical edge inference memory (vEIM), which will be integrated directly on top of processors.
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