ASE, the outsourced semiconductor assembly and test supplier, announced a 3D system-in-package solution built on its PowerSiP platform that vertically integrates the voltage regulator module (VRM) and shortens the current path. The company says the approach cuts parasitic wiring loss by more than half, citing advanced high-performance AI SoCs that exceed 1,000W and need peak currents above 1,000A at sub-1V voltages. The PowerSiP toolbox includes double-sided connected capacitors sandwiched between coreless substrates, capacitor array modules with exposed terminals, 4:1 high-aspect-ratio copper pillar integration, and single- or double-sided molded high-density active and passive component integration, aimed at fitting VRMs on the back side of PCBs in space-constrained compute trays.