Cadence

Headlines · 5

1. 3d
   TSMC A14 reportedly slated for mass production in first half of 2028

   Wccftech, citing DigiTimes, reports that TSMC's A14 process is planned to enter mass production in the first half of 2028, following risk production in the second half of 2027. Fab 20 and Fab 25 are named as the primary production sites. ETNews, as cited by Wccftech, reports that A14 is intended to scale SRAM bit cells from 0.021 µm² to 0.017 µm². DigiTimes also reportedly estimates that TSMC's 2028 A14 capacity could be 7.5 times Intel's 14A capacity; this figure is attributed to the report.

   Wccftech · 🔥 0
2. 6d
   Cadence launches Maestro models for chip design agents

   Cadence launched Maestro, a portfolio of domain-specialized AI models for its chip and system-design agents, with the first models planned for select early-access customers in Q4 2026. Customers can post-train the models on proprietary designs and workflows and deploy them in Cadence’s cloud, public clouds, or customer-controlled on-premises environments. Cadence claims initial results show up to 30% better result quality and fivefold token efficiency versus a general-purpose foundation model, but the company did not disclose how the quality figure was measured.

   Tom’s Hardware · 🔥 0
3. Oct 21
   NVIDIA shows agent-assisted OpenUSD workflow for AI factory digital twins

   NVIDIA published a technical blog post demonstrating an agent-assisted workflow that turns reference assets, site data and design requirements into an editable OpenUSD campus model. The workflow is built on the NVIDIA Omniverse DSX Blueprint, part of NVIDIA DSX Sim, which supplies reference digital twin assets, sample scripts and workflows built on OpenUSD and NVIDIA Omniverse libraries with SimReady assets. NVIDIA says frontier AI models can help developers work with this foundation through agents and connected tools, with developers guiding agents to assemble and revise OpenUSD scenes while engineers review results to inform the next design iteration. The post also references work by Dassault Systèmes, PTC, Cadence and Siemens on connecting design, product data and simulation tools to the digital twin.

   NVIDIA Technical Blog · 🔥 0
4. Oct 16
   IBM to open 0.7nm Nanostack process to chip designers with Q1 2027 PDKs

   IBM plans to make process development kits (PDKs) for its 0.7nm “Nanostack” chip manufacturing technology available in the first quarter of 2027, according to Wccftech. The kits are meant to let chip designers evaluate the 7-angstrom process and include design rule manuals, design rule checking and scripts for generating layouts through EDA tools from companies such as Cadence and Synopsys; the report says chip makers such as NVIDIA and AMD could use them to design products. IBM says Nanostack vertically stacks and staggers n-type and p-type transistors and claims 40% SRAM scaling, vendor claims that have not been independently verified.

   Wccftech · 🔥 0
5. Oct 14
   NVIDIA launches cuPotential CUDA-X library for AI-defined fabs

   At SEMICON West, NVIDIA introduced cuPotential, a new CUDA-X library developers can use to build AI agents that simulate how atoms and molecules interact; NVIDIA says early-access testing accelerated already GPU-optimized workflows by an additional 2-3x, with Synopsys among early adopters. NVIDIA also said Applied Materials, Cadence, KLA, Lam Research, Siemens and Synopsys are using its accelerated computing and AI stack across chip design, manufacturing and testing, citing NanoVDB helping Lam Research reach 30x faster simulation, NPP accelerating KLA inspection, and cuLitho delivering up to 20x speedups on optical proximity correction workloads. cuPotential is available in early access, NanoVDB ships as open source within OpenVDB, and NPP is available through the CUDA Toolkit.

   NVIDIA Newsroom · 🔥 0

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