SK hynix unveils H-TPU, a tiny SSD controller core it says draws 2.5% of a CPU core's power
SK hynix detailed an in-house processor architecture called the Hynix Transaction Processing Unit (H-TPU), presented by SoC design vice president Koo In-jae at the ISOCC 2026 conference in Songdo, Incheon on October 12. The company says H-TPU is not an AI tensor accelerator but a programmable processor for SSD data-plane and transaction control, using a simplified four-stage, in-order pipeline without superscalar or out-of-order units; it claims the core takes about 4% of a general-purpose CPU core's area and roughly 2.5% of its power. Instead of one monolithic CPU, SK hynix splits more than 100 repetitive functions — such as read/write command processing, metadata and buffer control — across dozens of small TPU clusters, activating only the modules a task needs while the traditional Arm CPU keeps management duties, per the reports. SK hynix plans to apply H-TPU across its NAND product lines, including next-generation enterprise SSD controllers, then in its next-generation AI storage architecture 'Storage Next', and expects synergies with its high bandwidth flash (HBF) due next year.
As AI data centers shift their bottleneck toward memory and storage, controller power and area limits matter; H-TPU is one bet that small purpose-built cores, rather than more general Arm cores, can keep scaling throughput.