Qualcomm validates first-generation HBC silicon for Dragonfly AI250
Qualcomm says its first-generation High Bandwidth Compute silicon completed hardware validation at its San Diego laboratory, including the full memory read-and-write path and near-memory computations. The company has taped out a data-center product using the architecture for the Dragonfly AI250 accelerator, which is expected to begin sampling in the first half of 2027. Qualcomm reports 133 TB/s of effective memory bandwidth for AI250, while its comparisons with LPDDR5X and projected HBM4 specifications are vendor-generated estimates rather than independent benchmarks.
The validation and tape-out mark a concrete hardware milestone for Qualcomm's effort to address memory bandwidth and data-movement constraints in data-center AI inference.
Qualcomm has completed testing the first chips built with its High Bandwidth Compute (HBC) memory technology, clearing a key step towards using it in data centre AI hardware. The company announced the results, saying the technology will feature in its Dragonfly AI250 accelerator, designed to run AI models in data centres.
Best known for its Snapdragon smartphone chips, Qualcomm introduced the Dragonfly brand for its data centre products in June. HBC is designed to address one of the main bottlenecks in running large language models at scale: moving data quickly enough between memory and processors.
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