PyTorch Helion taps Nvidia CompileIQ to tune ptxas compiler controls
A PyTorch blog post says Helion's kernel autotuner previously searched only tile shapes, warp counts, pipeline stages and memory access strategy, and can now also search ptxas compiler controls such as register allocation policy, fine-grained instruction scheduling and code-generation heuristics through Nvidia's CompileIQ, packaging results as portable Advanced Control Files (ACFs). In one example on a fixed, ahead-of-time-tuned NVFP4 GEMV kernel, an evolutionary CompileIQ search over eight generations with a pool of 15 candidates on GB200 cut execution time from 0.0971 ms to 0.0928 ms, a 1.047x (4.7%) speedup; the post stresses the gain is workload-specific and depends on shapes and architecture. Helion is open source under the PyTorch Foundation, while CompileIQ is proprietary but free to use under Nvidia's license, and the ACF files it produces are freely distributable.
The post argues that shipping kernels leave ptxas controls such as register allocation and instruction scheduling at defaults not because those defaults are optimal but because nothing has been searching them, and it frames the compiler's control surface as a searchable optimization space below already-tuned kernels.
With Helion’s release last year, it aimed at enabling developers to write GPU kernels in PyTorch-native Python and let its powerful autotuner do the work that used to require hand-written Triton and abstract away hardware-specific implementation details. Helion’s autotuner explores thousands of kernel configurations and routinely lands within a few percent of expert-tuned code, and oftentimes exceeding it.
The question that now needs to be answered is this: If a kernel has already been autotuned and optimized to the best of a developer’s ability, is there anything left?
There is. It lives below the kernel, in the compiler.
Every kernel autotuner in the ecosystem whether it is Helion’s, Triton’s, the one inside torch.compile, they all search the same thing: tile shapes, warp counts, pipeline stages, memory access strategy. All of those are decisions about what work each thread block does. Underneath them sits a second set of decisions about how that work becomes machine assembly instructions generated by ptxas, NVIDIA’s PTX assembler. Things like register allocation policy, fine-grained instruction scheduling, code-generation heuristics are left at their defaults for all kernels shipping today – not because the defaults are optimal, but because nothing was searching and optimizing them!
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