Nagare Labs advances Z2RAM memory-on-compute prototype
Nagare Labs says its Z2RAM could place SRAM-speed memory with DRAM-like density directly on AI accelerators, addressing bandwidth and heat constraints that make stacked HBM difficult. Founder papers report a three-transistor cell retaining data for more than 300 seconds at 85°C, while Gen 1 targets such as 5× SRAM density and 14× DRAM speed remain vendor projections. The technology remains a lab prototype without a fabrication facility, and no published cell has demonstrated retention above 95°C.
Z2RAM offers a possible memory-on-compute approach for AI accelerators, but its projected performance has not been demonstrated in a fab-built, multilayer stack.
A Pat Gelsinger-backed Georgia Tech spinout, Nagare Labs, says its Z2RAM can put SRAM-speed memory, at DRAM density, directly on top of AI chips. The founders’ own papers show a fast-improving cell that, tested up to 85 degrees Celsius, holds data for over 300 seconds. Gen 1 is projected to have 5x SRAM density with six stacked layers, 14x DRAM speed, and 3x less read energy than SRAM.
AI chips require a lot of bandwidth, and it has been challenging to get sufficient yields of high-bandwidth memory (HBM) to feed them. Even when manufacturers can get it, some reportedly plan to settle for fewer layers for yield reasons, and heat is another. Heat is also why Samsung’s zHBM, which stacks DRAM directly on the processor, is planned at only about four layers.
Alternatives include high-bandwidth flash, still in development, which stacks NAND like HBM and would sit beside the GPU, or SRAM stacked directly on the die, which is less dense and more expensive for the capacity, but also faster. DRAM, which is more capacious, can sit on top of the compute, but heat limits how hard the logic underneath can run.
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