Huawei details Kirin 9050 Pro, its first logic-folded chip, with on-device 30B MoE
At a 2026 Kirin media briefing in Shanghai on Oct 13, Huawei semiconductor executive Xu Songyu published the full architecture diagram of the Kirin 9050 Pro, the first logic-folded "Tao" chip, which Huawei says has been mass-produced with support from China's semiconductor industry. The chip combines a new Lingxi CPU (9 cores, 16 threads), a fourth-generation Maleoon GPU with second-generation hardware ray tracing (40% higher performance, 45% lower power, 78% better ray tracing), a new Da Vinci NPU, a Kirin AI ISP, a Balong AI Modem, an FFTS function-flow task scheduler, a security processor and the Lingxi micro-core. Huawei says the NPU raises AI performance by 140% while cutting power by 66% and enables the industry's first on-device 30B MoE model (2B active parameters, under 2.5GB of memory), alongside 7B dense and 1B VLM models; Xu also said the next-generation Kirin 2027 chip is ready and that all test results so far meet expectations.
Running a 30B MoE model on a phone-class NPU shows how far on-device AI is moving beyond small assistants, and signals Huawei's continued push on self-designed silicon despite supply-chain constraints.