AMD Zen 6 EPYC Venice Deep Dive and Benchmarks
Tom’s Hardware examined the Zen 6 architecture and tested AMD’s 256-core EPYC 9996 and 96-core EPYC 9686F on the SP7 platform. The report says Zen 6 introduces native FP16 instructions, while its two-IOD design gives SP7 access to 16 memory channels. In a two-socket configuration, the EPYC 9996 delivered 1,024 threads and scored 93% ahead of the 768-thread EPYC 9965 in the report’s SPEC CPU 2026 intrate throughput estimate. The frequency-optimized 9686F performed strongly in scientific-computing and HPC workloads. The SPEC results were not submitted to the SPEC committee and therefore remain estimates.
Zen 6 combines higher-throughput configurations with native FP16 support and a 16-channel memory platform, making it directly relevant to HPC, AI-host and other data-center workloads.
AMD’s EPYC ‘Venice’ CPUs are the first to debut the new Zen 6 architecture, and we’ve been testing two chips from the range over the past several weeks to see how they compare to Nvidia’s Vera, and more broadly, how the Zen 6 architecture departs from Zen 5 ahead of the expected consumer-focused Olympic Ridge launch next year. Zen 5 was a ground-up redesign of AMD’s storied Zen core, and Zen 6 takes that foundation and expands it in just about every regard.
Zen 6 uses TSMC’s N2P node, but it also comes with significant architectural changes under the hood. Within the core, a redesigned vector engine pushes AMD’s SIMD performance even higher, and it now natively supports half-precision FP16 instructions alongside full, 32-bit precision. It also splits integer schedulers within the execution engine, allowing for more instructions in flight through the core.
Across the die, AMD made other significant changes. The single IOD of previous generations is now split across two IODs, giving the SP7 platform access to 16 memory channels (though at the cost of PCIe 6.0 lanes compared to the previous generation and SP8 platform).
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