Huawei details Kirin 9050: Tao's Law, logic folding, hybrid bonding
Chinese outlet Zhidx reports that Huawei held a two-day technical briefing in Shanghai, its first detailed public explanation of its Kirin chips in six years. Huawei says the Kirin 9050 series is the first to use "logic folding," with hybrid bonding pitch of 1.5 microns and more than 50 million high-speed channels, claiming gains of 12.7% in CPU clock speed, 40% in GPU performance, 140% in NPU compute and 41%-66% in energy efficiency. Huawei also described multi-level memory-compute coordination and a joint quantization scheme that runs a 30B model on-device in about 2.5GB of memory, and said the test metrics for "Kirin 2027" all met expectations.
It is Huawei's first systematic public account of its chip roadmap after losing access to advanced process nodes; if logic folding scales, it could offer a new performance and efficiency path for on-device AI models.